21
LTC1968
1968f
APPLICATIO S I FOR ATIO
U
U
U
This allows each sample to settle to within 46ppm and it is
these samples that are used to compute the RMS value.
This is a much higher accuracy than the LTC1968 conver-
sion limits, and far better than the accuracy computed via
the simplistic resistive divider model:
Output Impedance
The LTC1968 output impedance during operation is simi-
larly due to a switched capacitor action. In this case, 20pF
of on-chip capacitance operating at 2MHz translates into
25k&. The closed-loop RMS-to-DC calculation cuts that in
half to the nominal 12.5k& specified.
In order to create a DC result, a large averaging capacitor
is required. Capacitive loading and time constants are not
an issue on the output.
However, resistive loading is an issue and the 10M&
impedance of a DMM or 10?scope probe will drag the
output down by 0.125% typ.
During shutdown, the switching action is halted and a
fixed 12.5k resistor shunts V
OUT
to OUT RTN so that C
AVE
is discharged.
Interfacing with an ADC
The LTC1968 output impedance and the RMS averaging
ripple need to be considered when using an analog-to-
digital converter (ADC) to digitize the LTC1968 RMS
result.
The simplest configuration is to connect the LTC1968
directly to the input of a type 7106/7136 ADC as shown in
Figure 21a. These devices are designed specifically for
DVM/DPM use and include display drivers for a 3 1/2 digit
LCD segmented display. Using a dual-slope conversion,
the input is sampled over a long integration window, which
results in rejection of line frequency ripple when integra-
tion time is an integer number of line cycles. Finally, these
parts have an input impedance in the G& range, with
specified input leakage of 10pA to 20pA. Such a leakage,
combined with the LTC1968 output impedance, results in
less than 1礦 of additional output offset voltage.
Another type of ADC that has inherent rejection of RMS
averaging ripple is an oversampling ?ADC such as the
LTC2420. Its input impedance is 6.5M&, but only when it
is sampling. Since this occurs only half the time at most,
if it directly loads the LTC1968, a gain error of 0.08% to
0.11% results. In fact, the LTC2420 DC input current is
V V
R
R R
V
M
V
IN SOURCE
IN
IN SOURCE
SOURCE
SOURCE
=
+
=
&
=
1.2
125
. %
M k
&+
1.2 15.5 &
This resistive divider calculation does give the correct
model of what voltage is seen at the input terminals by a
parallel load averaged over a several clock cycles, which is
what a large shunt capacitor will doaverage the current
spikes over several clock cycles.
When high source impedances are used, care must be taken
to minimize shunt capacitance at the LTC1968 input so as
not to increase the settling time. Shunt capacitance of just
0.8pF will double the input settling time constant and the
error in the above example grows from 46ppm to 0.67%
(6700ppm). As a consequence, it is important to not try to
filter the input with large input capacitances unless driven
by a low impedance. Keep time constant <<125ns.
When the LTC1968 is driven by op amp outputs, whose
low DC impedance can be compromised by sharp capaci-
tive load switching, a small series resistor may be added.
A 1k resistor will easily settle with the 0.8pF input sampling
capacitor to within 1ppm.
These are important points to consider both during design
and debug. During lab debug, and even production testing,
a high value series resistor to any test point is advisable.
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